This relates to integrated circuits and more particularly, to systems for designing logic circuitry on integrated circuit devices such as programmable integrated circuits.
Programmable integrated circuits are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design tools to design a custom logic circuit that performs custom logic functions. When the design process is complete, the computer-aided design tools generate configuration data. The configuration data is loaded into memory elements to configure the devices to perform the functions of the custom logic circuit. Memory elements are often formed using random-access-memory (RAM) cells. Because the RAM cells are loaded with configuration data during device programming, the RAM cells are sometimes referred to as configuration memory or configuration random-access-memory cells (CRAM).
Integrated circuits such as programmable integrated circuits often include millions of gates and megabits of embedded memory. The complexity of a large system requires the use of electronic design automation (EDA) tools to create and optimize a logic design for the system onto an integrated circuit (target device). The tools may perform logic synthesis operations to generate a gate-level description of the logic design for implementation on a target programmable logic device. Logic synthesis also performs technology mapping to map the gates onto logic elements (resources) that are available on the target programmable logic device. These include, but are not limited to, lookup-tables (LUTs), flip-flops, block RAMS, and digital signal processing (DSP) elements. The logic elements are then placed and routed onto the target programmable device, while concurrently optimizing for timing, area, wiring, routing congestion, and power.
Synthesized designs are also subject to design constraints sometimes referred to herein as legality rules. The legality rules identify acceptable (“legal”) placements for logic elements in the design. The tools perform timing analysis and other tests to determine whether the legality rules and timing constraints are satisfied in a process sometimes referred to herein as legalization.
Conventionally, physical synthesis is performed either before or after the placement phase in a design implementation flow. The tools then perform legalization after the post-placement physical synthesis. If the legality rules are not satisfied, all changes made by physical synthesis are scrapped even when only a small subset of the changes cause legalization errors. Furthermore, if the legalization succeeds, it is often possible that the timing of the design itself has deteriorated because the logic elements may have moved large distances to satisfy the legality rules. Performing legalization in this way can lead to excessive runtimes as well as fail to meet the timing constraints of the design.